1. Field of the Invention
The present invention relates to a communication apparatus for processing a connection.
2. Description of the Related Art
Along with the prevalence of Gigabit Ethernet(R) and the like, not only general-purpose PCs but also embedded devices are required to execute network protocol processing at high speed.
In order to achieve the Full-wire speed of Gigabit Ethernet(R), a processor with an operating frequency of about 3 GHz is required. Such operating frequency is far beyond the performances of processors normally equipped in embedded devices. Hence, it is becoming increasingly popular to realize broadband network communications by adding, to a system, an auxiliary device such as a TOE (TCP/IP Offload Engine) specialized to protocol processing. An example of the prior art of the TOE is disclosed in WO0013091.
PCB handling is important in TCP protocol processing. A PCB is an abbreviation for a protocol control block. The PCB is context information configured by several ten types of parameters (variables) prepared for each TCP connection, and which PCB information is to be used must be looked up and determined every time a TCP packet is received.
Elements of each PCB are variables which are frequently accessed during TCP processing, i.e., keystone variables in the TCP processing. Upon speeding up of TCP, speeding up of PCB lookups and accesses is indispensable.
In the invention disclosed in WO0013091, a high access speed is realized by copying and holding a PCB required to execute the TCP protocol processing from a main memory to a high-speed temporary memory such as an SRAM or the like. At this time, when the number of connections increases, and all PCBs cannot fall within the temporary memory, replacement processing is executed between the temporary memory and main memory so that temporary memory holds only required PCBs.
As described above, by storing and processing PCBs in a high-speed temporary memory, protocol stack processing can be speeded up. However, in consideration of the processing performance, the influence of the replacement processing of the PCBs in the temporary memory must be taken into consideration. The replacement of PCBs in the temporary memory frequently occurs when the capacity of the temporary memory is smaller than the number of connections. This problem is serious in a system of embedded devices since the capacity of the temporary memory cannot be increased in terms of cost.
Upon replacing PCBs in the temporary memory, one of PCBs stored in the temporary memory is selected, is written back to the main memory, and a newly required PCB is then read out. Since the data size of a PCB is as large as a hundred and several ten bytes, a time period required for the temporary memory replacement imposes a serious influence on the system performance. Hence, it is demanded to shorten this time period.